Indian Patent SCI Journal MAC Unit CRC Press VLSI Design Low Power RTL-to-GDSII Taylor & Francis FPGA CNN Under Review VIT Chennai Book Chapter Cadence Genus Softmax Verilog HDL Patent Office Multiplier ISBN Smart Buildings

RESEARCH OUTPUT

Publications

A record of research contributions spanning VLSI design, low power circuits, and semiconductor applications. Manuscripts communicated to respective offices and journals.

PUBLICATIONS

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2 PATENTS 2 JOURNAL PAPERS 1 BOOK CHAPTER 1 RESEARCH ARTICLE

PATENT

Status : Published 2nd Inventor

Dynamic Reconfigurable Binary Multiplier System and Method Thereof

Application No.: 202541080342 · Published: 19 September 2025 · Institution: Vellore Institute of Technology, Chennai

Inventors Dr. S. Umadevi, Preetham SK, Nakul S, Sumit Kumar

Presents a dynamically reconfigurable binary multiplier capable of automatically scaling across different operand bit-widths. The architecture uses quadrant decomposition and an adaptive row bypassing scheme to disable partial product rows for zero-valued multiplicand bits — reducing dynamic switching activity and power dissipation without compromising computational accuracy. Implemented in Verilog HDL with complete RTL-to-GDSII flow using Cadence Genus and Cadence Innovus across TSMC 180nm and 90nm CMOS technology nodes.

PATENT

Status : Under Review First Inventor

Low-Power High-Performance Fixed-Point Softmax Processing Unit with LUT-Based Exponent and Mitchell Logarithmic Divider

Institution: Vellore Institute of Technology, Chennai

Inventors Preetham SK, Sreehari R, Dr. P. Sasipriya, Dr. A. Anita Angeline, Prof. V. Anantha Krishnan

Discloses a fully fixed-point hardware architecture for the Softmax activation function targeting DNN inference accelerators. The architecture comprises a dual-mode LUT-based Exponent Block (Single-LUT with 61 entries and linear interpolation; Dual-LUT with cascaded multiplicative tables), a 36-bit Q22.14 Accumulator Block, and an 8-stage fully pipelined Mitchell Logarithmic Division Block — achieving one output per clock cycle with 8.9× throughput improvement over sequential dividers. Validated at 100 MHz on TSMC 180nm with 97.89% MNIST classification accuracy and 100% hardware-software output match across 10,000 samples.

SCI JOURNAL PAPER

Status : Under Review 2nd Author

Adaptive Quadrant Multiplier with Dynamic Reconfigurable Structure

Venue: SCI-Indexed Journal · Institution: Vellore Institute of Technology, Chennai

Authors Adhiyamaan, Preetham SK, Dr. S. Umadevi, Ms. Rekha

Proposes an Adaptive Quadrant (AQ) multiplier with dynamic reconfigurable structure, evaluated across TSMC 180nm and 90nm CMOS technology nodes. AQ1 uses a Ripple Carry Adder for area and power efficiency; AQ2 uses a three-segment hybrid prefix adder (Han-Carlson, Weinberger, Ling) for high-speed performance. At 90nm, AQ1 achieves 98.92% lower power, 28.19% smaller area, and 98.47% improved Power Delay Product compared to existing 16-bit multipliers. Technology scaling from 180nm to 90nm results in 83.45% power reduction and 68.04% area reduction. Post-layout results from Cadence Innovus confirm timing closure with positive slack across all configurations.

BOOK CHAPTER

Status : Accepted for Publication 2nd Author

FPGA Based Solar Powered EV Charging Station — Smart Infrastructure for a Sustainable Future

Type: Book Chapter · Book: Smart Technologies for Smart Buildings · Publisher: CRC Press, Taylor & Francis Group
ISBN: 9781041093626 · Agreement Signed: February 2026 · Institution: Vellore Institute of Technology, Chennai

Authors Nakul S, Preetham SK, Pradeesh R, Kartheesan K, Dr. Gnana Swathika OV

Presents an FPGA-based control system for a Solar Powered EV Charging Station. An 11-state FSM-based controller was designed in Verilog HDL to manage charge states, fault detection, and power routing logic. Implements the Perturb & Observe (P&O) MPPT algorithm for maximum solar power extraction under variable irradiance. Functional simulation and waveform verification performed using ModelSim. FPGA-based control achieves 15% peak demand reduction, power factor >0.95, and 8× faster decision-making than PLC.

REVIEW ARTICLE

Status : Under Review First Author

Convolutional Neural Networks on Dedicated Hardware: A Comprehensive Survey of VLSI, FPGA and ASIC Implementations Across Real World Application Domains

Venue: Journal · Institution: Vellore Institute of Technology, Chennai

Authors Preetham SK, Dr. Lavanya V, Dr. Meera P S

Comprehensive survey of CNN hardware acceleration across image processing, ADAS, medical imaging, IoT/industrial robotics, and smart surveillance. Consolidates quantitative results from FPGA, ASIC, and VLSI implementations into unified comparison tables. Key contribution: cross-domain comparative analysis identifying generalisable optimisation strategies (quantisation, pruning, hardware-software co-design) versus domain-specific techniques. Benchmarks include 587.52 GOPs at 142.95 GOPs/W (image processing FPGA), 25.4 fps across 4 ADAS tasks, and 1.145 TFLOP/s at 34.9 µW (medical wearable ASIC).

SCI JOURNAL PAPER

Status : Work In Progress First Author

Silicon-Level Implementation and Performance Characterisation of a Fixed-Point Softmax Processing Unit for DNN Inference Accelerators

Venue: SCI-Indexed Journal · Institution: Vellore Institute of Technology, Chennai

Authors Preetham SK, Sreehari R, Dr. P. Sasipriya, Dr. A. Anita Angeline, Prof. V. Anantha Krishnan

Extends the fixed-point Softmax hardware architecture into a full ASIC implementation with complete RTL-to-GDSII physical design on TSMC 180nm using Cadence Innovus. Both Single-LUT (5,152 cells, 132,703 µm², 13.44 mW, 171 ps slack) and Dual-LUT (5,026 cells, 132,969 µm², 12.14 mW, 68 ps slack) configurations implemented through floorplanning, placement, CTS, routing, SPEF extraction, and GDSII generation. Functional verification achieves 97.89% MNIST accuracy with 100% hardware-software match across 10,000 samples.