IEEE VLSI Design Technical Writing VDAT 2024 FPGA ASIC Design Flow Cadence HDL Symposium The Spectrum VIT Chennai Editorial DFT CMOS Workshop TechnoVIT EE Magazine Volunteer Student Chapter VIT Vellore
BEYOND THE CURRICULUM

Extracurricular

Technical journalism, professional volunteering, symposia, and hands-on workshops — activities that shaped both my engineering breadth and collaborative instincts.

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ACTIVITIES
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1 EDITORIAL ROLE 1 IEEE MEMBERSHIP 1 SYMPOSIUM 3 WORKSHOPS
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EDITORIAL — 2022 TO 2025
Editor — The Spectrum
School of Electrical Engineering  ·  Annual Technical Magazine  ·  VIT Chennai
Editorial Board  ·  Technical Content Curation & Editing
2022 — 2025
ROLE
Edited and curated technical content for the School of Electrical Engineering's annual magazine across three volumes, reviewing articles, ensuring technical accuracy, and maintaining editorial standards throughout the publication cycle.
SCOPE
Content spanned the breadth of the electrical engineering curriculum — VLSI, embedded systems, power electronics, signal processing, and emerging semiconductor technologies contributed by students and faculty.
IMPACT — Contributed to three consecutive volumes of the EE department's flagship publication, developing technical communication skills alongside the engineering curriculum. Click any volume below to open it.
Technical Editing Content Curation Science Communication VIT Chennai EE Department
VOLUME 01
The Spectrum
VIT Chennai  ·  School of EE  ·  Annual Magazine
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VOLUME 02
The Spectrum
VIT Chennai  ·  School of EE  ·  Annual Magazine
OPEN PDF
VOLUME 03
The Spectrum
VIT Chennai  ·  School of EE  ·  Annual Magazine
OPEN PDF
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PROFESSIONAL MEMBERSHIP — 2022 TO 2023
IEEE Student Chapter — VIT Chennai
Institute of Electrical and Electronics Engineers  ·  Volunteer Member
Student Branch  ·  VIT Chennai Campus
2022 — 2023
INVOLVEMENT
Active volunteer member of the IEEE Student Chapter at VIT Chennai, the world's largest technical professional organisation for electrical and electronics engineers. Participated in chapter events, technical talks, and student-led initiatives.
CONTEXT
Membership provided access to IEEE Xplore technical literature, networking with industry professionals, and exposure to current research directions in electrical engineering and semiconductor technology.
IEEE Student Chapter Volunteer VIT Chennai
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SYMPOSIUM — SEP 2024
VDAT 2024 — International Symposium on VLSI Design and Test
28th Edition  ·  VIT Vellore  ·  Attendee
International Symposium  ·  VLSI Design, Test & Verification
SEP 2024
EVENT
Attended the 28th International Symposium on VLSI Design and Test held at VIT Vellore — one of India's premier academic forums on VLSI chip design, test methodologies, verification, and semiconductor research.
EXPOSURE
Engaged with cutting-edge research presentations, industry sessions on EDA tools, and academic talks covering physical design, low-power techniques, and advanced test strategies — directly relevant to graduate-level VLSI research.
VLSI Design VDAT 2024 Symposium VIT Vellore Test & Verification
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VDAT 2024 Participation Certificate
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WORKSHOPS — 2023 TO 2024
HDL Based ASIC Digital Design Flow
TechnoVIT'24  ·  VIT Chennai  ·  Workshop
Hands-On Workshop  ·  HDL & ASIC Design Methodology
SEP 2024
CONTENT
Workshop covering the end-to-end ASIC digital design flow using Hardware Description Languages — RTL specification, simulation, synthesis, and sign-off — through hands-on sessions reflecting an industry-standard ASIC design methodology.
RELEVANCE
Directly reinforced skills from ongoing coursework and project work in digital VLSI design, particularly the OpenLANE RTL-to-GDSII flow and VSDSYNTH TCL automation.
HDL ASIC Design TechnoVIT'24 RTL to GDSII Workshop
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HDL ASIC Design Flow Workshop Certificate
Fundamentals of Design for Testing using Cadence
SENSE-bandVIT  ·  VIT Chennai  ·  Workshop
Hands-On Workshop  ·  DFT Methodology & Cadence EDA
SEP 2024
CONTENT
Practical workshop on Design for Testability (DFT) fundamentals — scan insertion, ATPG, boundary scan, and fault coverage analysis using Cadence EDA toolchain, reflecting industry practice for chip verification and test closure.
TOOLS
Hands-on exposure to Cadence tools for DFT flow, supplementing physical design and layout knowledge with a test-oriented perspective essential for tape-out-ready design.
DFT Cadence Scan Insertion ATPG SENSE-bandVIT
HOVER TO VIEW CERTIFICATE
DFT Cadence Workshop Certificate
Programming with FPGA for EE System Design
VIT Chennai  ·  Workshop
Hands-On Workshop  ·  FPGA Programming & Digital System Design
OCT 2023
CONTENT
Workshop on FPGA-based digital system design for electrical and electronic applications — covering HDL-based FPGA programming, constraint setting, place-and-route, and hardware deployment for real-world EE systems.
SKILLS
Practical experience with FPGA toolchains (Vivado), hardware description at the register-transfer level, and mapping digital designs to programmable logic fabric — bridging theoretical RTL knowledge with physical hardware implementation.
FPGA Vivado Digital Design HDL Programming Place & Route
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FPGA Workshop Certificate
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