Cadence Innovus RTL-to-GDSII Sky130 PDK OpenLANE Verilog HDL RISC-V RV32I Place & Route STA HSPICE TL-Verilog DRC / LVS Magic VLSI Yosys VHDL Floorplanning SystemVerilog OSU 0.18µm ModelSim ANSYS CTS

Preetham
SK

A curious engineer drawn to the intersection of physics and logic, where transistors become processors and silicon becomes intelligence. Passionate about chip design and committed to building a career in semiconductor engineering.

B.Tech EEE — Vellore Institute of Technology MS Applicant — Germany 🇩🇪
9.18
CGPA / 10
1.4
DE SCALE
6
PUBLICATIONS
7
PROJECTS
4
INTERNSHIPS
DOWNLOAD CV EXPLORE PROFILE
TECH NODE 130nm / 180nm
STANDARD CELLS 3,106 cells
STATUS DRC ✓  LVS ✓
TOOL CHAIN Cadence / Yosys
PDK Sky130 / OSU 0.18µm
CLK
EN
ABOUT ME

Who Am I

I am a final-year B.Tech Electrical and Electronics Engineering student at VIT Chennai, with a deep interest in VLSI design and semiconductor engineering. What draws me to this field is the elegance of making complex systems work at the physical level — writing RTL that eventually becomes a fabricated circuit, and understanding every step in between.

I have completed four internships across physical design, RTL development, and research, contributed to a published Indian patent, a CRC Press book chapter, and submitted journal manuscripts. I am currently applying for Masters programmes in Germany to deepen my expertise in VLSI and semiconductor research.

RTL Design Physical Design Logic Synthesis STA & Timing RISC-V SPI / UART / I2C Cadence Genus OpenLANE Sky130 PDK HSPICE / SRAM Verilog / TL-V VHDL
Preetham SK
WEN
SEL
EDUCATION

Academic Background

Vellore Institute of Technology (VIT) Chennai
B.Tech — Electrical and Electronics Engineering
CGPA: 9.18 / 10  ·  German Equivalent: 1.4
Sep 2022 – May 2026
Chennai, India
Senthil Public School, Jagirammapalayam
Class XII · CBSE
85.0%
2022
Salem, India
Sri Swamy International School, Ayothiyapattanam
Class X · CBSE
93.0%
2020
Salem, India
DATA
ADDR
SKILL SUMMARY

Skills Summary

EDA TOOLS
Cadence NC LaunchCadence Genus OpenLANEMagic VLSI YosysQflow NetgenModelSim OpenTimerVesta STA
HDL & LANGUAGES
Verilog HDLTL-Verilog VHDL TCL ScriptingPython C / Embedded C
DESIGN FLOW
RTL DesignLogic Synthesis FloorplanningPlace & Route CTSSTA DRC / LVSGDSII Sign-off
SIMULATION TOOLS
ANSYS ElectronicsANSYS Mechanical HSPICELT Spice Makerchip IDEMATLAB / Simulink Keil µVision 5
PROTOCOLS & ARCHITECTURE
RISC-V RV32ISPI Master/Slave UART (FSM)I2C AXI / APB BusSky130 PDK OSU 0.18µmFPGA (Xilinx)
DESIGN & CAD TOOLS
Eagle CADKiCAD MATLAB / Simulink LinuxArduino
RST_N
VALID
DOCUMENTATION

Explore My Profile

01 — PUBLICATIONS
VIEW ALL →
  • Dynamic Reconfigurable Binary Multiplier — Indian Patent (Published Sep 2025)
  • Low Power VLSI Design — Patent Under Review
  • 16-Bit MAC Unit — SCI Journal Under Review
  • Low Power VLSI Design — SCI Journal Under Review
  • FPGA Based Solar Powered EV Charging Station — CRC Press Book Chapter
  • CNN Application — Research Article Under Review
02 — PROJECTS
VIEW ALL →
  • Digital VLSI SoC Design & Planning
  • Advanced SRAM Memory Design (7T / 8T)
  • RISC-V CPU Design using TL-Verilog
  • VLSI Design Automation using TCL — VSDSYNTH
  • SPI Physical Design using Qflow
  • RTL Digital Design Modules — Verilog
  • Packaging Design & Simulation using ANSYS
03 — INTERNSHIP
VIEW ALL →
  • Maven Silicon — VLSI Physical Design Intern
  • CNVD, VIT Chennai — Summer Research Intern
  • CSGT, VIT Chennai — Summer Research Intern
  • SkillDzire — VLSI Design Intern
04 — CERTIFICATIONS
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  • CeNSE Winter School — Certificate of Distinction (IISc Bengaluru)
  • Chip-based VLSI Design Specialisation (L&T EduTech / Coursera)
  • Fundamentals of Digital Design for VLSI Chip
  • VLSI Chip Design with Electric VLSI Tool
  • Design of Digital Circuits with VHDL
  • RISC-V Processor RV32I Base ISA (Maven Silicon)
05 — AWARDS
VIEW ALL →
  • Danfoss Innovator Award 2025 — Finalist
  • Robooceana Grand Finale — Certificate of Excellence (IIT Madras, Shaastra 2024)
06 — EXTRACURRICULAR
VIEW ALL →
  • Editor — The Spectrum, VIT Technical Magazine (2022–2025)
  • IEEE Student Chapter — Volunteer Member
  • VDAT 2024 — 28th Int. Symposium on VLSI Design and Test
  • HDL-based ASIC Design Flow — TechnoVIT'24
  • Fundamentals of Design for Testing using Cadence
  • Programming with FPGA for EE System Design
MOSI
MISO