RTL-to-GDSII OpenLANE Sky130 PDK RISC-V RV32I Verilog HDL TL-Verilog Place & Route TCL Scripting HSPICE ANSYS Magic VLSI Floorplan CTS Timing Closure Qflow GDSII Standard Cell STA Wire Bonding

ENGINEERING WORK

Projects & Implementations

Hands-on implementations spanning the full VLSI design stack — from RTL coding and logic synthesis to physical design, timing closure, and fabrication-ready GDSII generation.

PROJECTS

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2 GDSII 1 RISC-V 1 TCL AUTO 1 PACKAGING 1 RTL MODULES

PHYSICAL DESIGN

COMPLETED RTL-TO-GDSII SKY130 PDK

Digital VLSI SoC Design & Planning

Verilog · OpenLANE · Sky130 PDK · Magic VLSI · OpenTimer

IMPLEMENTATION

Complete RTL-to-GDSII physical design flow on PicoRV32a RISC-V processor — synthesis, floorplan, placement, CTS, routing, and STA using OpenLANE on Sky130 PDK.

CUSTOM CELL

Designed and integrated custom standard cell sky130_vsdinv; timing closure achieved via ECO flow; DRC/LVS clean; fabrication-ready GDSII generated.

CPU DESIGN

COMPLETED RISC-V RV32I TL-VERILOG

RISC-V CPU Design using TL-Verilog

TL-Verilog · Makerchip IDE · RISC-V RV32I ISA

IMPLEMENTATION

Designed a 5-stage pipelined RISC-V RV32I core from scratch in TL-Verilog — fetch, decode, execute, memory, and writeback stages built progressively.

FEATURES

Data hazard bypassing logic, branch control, instruction and data memory integration; fully verified on Makerchip IDE with waveform simulation.

DESIGN AUTOMATION

COMPLETED TCL YOSYS · OPENTIMER

VLSI Design Automation using TCL — VSDSYNTH

TCL · Yosys · OpenTimer · Shell Scripting · Linux

IMPLEMENTATION

Built VSDSYNTH — a fully automated, design-agnostic RTL-to-QoR framework. CSV-driven configuration, automated SDC constraint generation, Yosys synthesis, and OpenTimer STA execution — all from a single command.

VALIDATION

Validated on openMSP430 — 6845 gates synthesised, hierarchy check passed; professional QoR dashboard and CSV report auto-generated.

PHYSICAL DESIGN

COMPLETED QFLOW OSU 0.18µm

SPI Controller — Timing Closure and Physical Sign-off

Qflow · Yosys / ABC · Graywolf · Qrouter · Magic · Netgen · Vesta STA

IMPLEMENTATION

RTL-to-GDSII physical design of SPI controller using open-source Qflow EDA toolchain on OSU 0.18µm standard cell library — synthesis, placement, STA, and routing.

VERIFICATION

DRC/LVS clean using Magic and Netgen; 3,106 cells placed, 22,417 routes completed; fabrication-ready GDSII generated.

RTL DESIGN

COMPLETED VERILOG HDL MODELSIM

RTL Digital Design Modules using Verilog

Verilog HDL · ModelSim · FSM Design · UART / FIFO

5 MODULES DESIGNED

UART (parameterized, FSM-based, parity-checked) · Synchronous FIFO (configurable width/depth) · Traffic Light Controller (sensor-driven FSM with priority logic) · Automatic Temperature Controller · Washing Machine Controller.

VERIFICATION

Structured testbenches developed for all 5 modules; functional simulation and waveform verification performed using ModelSim.

SEMICONDUCTOR PACKAGING

COMPLETED ANSYS FLIP-CHIP · QFN

Packaging Design and Simulation using ANSYS

ANSYS Electronics Desktop · ANSYS Mechanical · Flip-Chip BGA · QFN

SIMULATION

Thermal simulation of flip-chip BGA packages in ANSYS Electronics Desktop; thermo-mechanical reliability analysis in ANSYS Mechanical for stress and deformation study.

MODELLING

3D package cross-section modelling — die, substrate, wire bonds, and encapsulation; comparative study of wire bonding, flip-chip, and QFN packaging methodologies.